Drake Enterprises

Logic Simulation, Part 1

Posted on Tue 23 May 2023 in Logic • Tagged with Logic, Simulation, SimPy

First steps with logic simulation using SimPy and pyvcd

Posted on Fri 09 October 2020 in Logic • Tagged with Logic, Math, Verilog

How to implement the geometric probability distribution in SystemVerilog

Posted on Sun 02 August 2020 in Logic • Tagged with Logic, Protocol, Verilog

An introduction to the ready/valid data transfer protocol

Posted on Mon 29 June 2020 in Logic • Tagged with Logic, Verilog

Explore the obscure yet powerful Verilog case "inside" statement

Posted on Tue 12 May 2020 in Blog • Tagged with Philosophy

Advice on avoiding the road to self destruction

Posted on Sat 23 August 2014 in Logic • Tagged with Logic, Verilog

Proper use of Verilog flop macros, and their surprising tradeoffs